FIG. 1 shows a delay-locked loop (DLL) 101 of the prior art (see U.S. Pat. No. 6,239,634 to McDonagh, for example). The DLL 101 comprises a phase frequency detector (PFD) 103, a charge pump 105, a loop filter (loop capacitor) 107 and a voltage controlled delay line (VCDL) 109. The VCDL 109 can include n stages, each stage contributing a certain amount of delay to the overall delay. The DLL 101 receives a reference clock signal (input clock signal) 111 and generates an output clock signal 113 that has its phase delayed by a fraction of a period of the reference clock signal 111.
The PFD 103 receives, on its input terminals, the reference clock signal 111 and the output clock signal 113. In a conventional arrangement, the PFD 103 is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, the PFD 103 generates one of three states. If the phases of the two signals differ by the desired amount, then the loop is “locked”. Neither the UP nor the DOWN signal is asserted and the delay of the VCDL remains the same. If the reference clock signal 111 leads the output clock signal 113 by more than the desired amount, then the delay of the DLL 101 is too much. If the reference clock signal 111 lags the output clock signal 113 by more than the desired amount, then the delay of the DLL 101 is too little. The detector 103 then outputs an UP or a DOWN signal (depending on the particular circuit design) proportional to the phase difference between the reference clock signal 111 and the output clock signal 113. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals. The UP and DOWN signals are output to the charge pump 105 through two separate lines.
The charge pump 105 generates a current Icp 115 that controls the voltage of the loop filter 107 and thereby the delay of the VCDL 109. The current 115 is dependent on the signal output by the PFD 103. If the charge pump 105 receives an UP signal from the PFD 103, Icp 115 is increased. If the charge pump 105 receives a DOWN signal from the PFD 103, Icp 115 is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals have the desired phase difference, the charge pump 105 does not adjust Icp 115.
The loop filter 107 is positioned between the charge pump 105 and the VCDL 109. An UP signal from the PFD 103 results in an increase of the voltage Vloop 117 on the loop filter 107, while a DOWN signal from the PFD 103 results in a decrease of the voltage Vloop 117 on the loop filter 107. Vloop 117 is applied to the VCDL 109. The VCDL 109 can be comprised of a voltage-to-current converter, which then supplies a current to a current controlled delay line to control the delay. The loop filter 107 also removes out-of-band, interfering signals before application of Vloop 117 to the VCDL 109. A common configuration for the loop filter 107 in the DLL 101 is a simple single-pole, low-pass filter that can be realized with a single capacitor.
The output clock signal 113 is looped back to the PFD 103 to facilitate the delay-locked loop operation. The DLL 101 thus compares the reference clock signal 111 phase to the output clock signal 113 phase and adjusts the detected phase difference between the two to a desired amount by adjusting the delay of the VCDL 109.
The prior-art DLL 101 faces lock problems. In order to prevent a false lock to a zero or incorrect phase, the initial state of the DLL 101 must be well defined so that the leading edge of the output clock signal 113 is delayed between ½ a period and 1½ periods. Additionally, a reset signal must be applied if the input frequency is changed.
FIG. 4 illustrates the lock-to-zero problem of the prior art. As can be seen, the fed-back output clock signal 113 has a phase, which is delayed by a small amount relative to the reference clock signal 111. The PFD 103 outputs an up signal 403 to the charge pump 105, increasing the voltage Vloop 117 in order to decrease the delay of the fed-back output clock signal 113. However, the Vloop 117 cannot increase enough and the DLL 201 becomes stuck, or locked-to-zero trying to achieve the zero phase delay.
FIG. 6 illustrates the false locking of the prior-art DLL. Due to the false locking, the reference clock signal 111 has a phase, which is delayed relative to fed-back output clock signal 113. The PFD 103 outputs a down signal 503 to the charge pump 105, decreasing the voltage Vloop 117 in order to increase the delay of the fed-back output clock signal 113.
McDonagh provides a circuit providing correct start-up and locking of the DLL circuit, but still requires that the DLL be biased to the smallest delay value. If the reference clock signal frequency is changed, then the DLL needs to be reset.
It would be desirable to have a DLL that would, without being reset, achieve correct startup and lock to the correct phase even if the reference clock signal frequency is changed.